1. Field of the Invention
The invention relates to data processors using watchdog timers.
2. Description of the Related Art
A watchdog timer is a timer which is continuously running while the data processor (computer) is operating and which causes a system reset if the timer reaches a predetermined value. In normal use the primary operating routine of the computer is arranged to reset the timer at intervals, so that if the computer is operating satisfactorily the timer never reaches its predetermined value. However, if an error should occur which results in the computer executing an endless sub-loop, the timer is not reset and continues to count to its predetermined value, at which point the endless loop is exited by the system reset.
A known computer system employing a watchdog timer is shown in FIG. 1. The computer is arranged to execute its primary operating routine cyclically and to jump from the primary routine to sub-routines (in order to perform specific tasks) as necessary. The primary routine contains, at predetermined locations, instructions to reset the watchdog timer. The positions within the primary routine of these instructions to reset the watchdog timer are so chosen that in normal operation of the computer the watchdog timer does not reach its predetermined count (and so cause a system reset) between any two consecutive instructions to reset the watchdog timer. Thus, if an error occurs in a sub-routine (e.g. a repetitive call to the sub-routine from within itself), the watchdog timer will not be reset and will reach its predetermined count, so causing a system reset.
Such watchdog timers are well known. However, it is still possible for such a watchdog timer to be "fooled" if, for example, an endless sub-routine (which should cause the timer to reach its predetermined count) also contains an instruction to reset the watchdog timer. In such a case the watchdog timer is continually reset in the endless sub-routine, which carries on executing indefinitely.